Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology - Equipe Secure and Safe Hardware Accéder directement au contenu
Pré-Publication, Document De Travail Année : 2019

Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology

Résumé

In this paper we present quaternary and ternary routing tracks for FPGAs, and their implementation in 28nm FDSOI technology. We discuss the transistor level design of multi-valued repeaters, multiplexers and translators, and specific features of FDSOI technology which make it possible. Next we compare the multi-valued routing architectures with equivalent single driver two-valued routing architectures. We show that for long tracks, it is possible to achieve upto 3x reduction in dynamic switching energy, upto 2x reduction in routing wire area and 10% reduction in area dedicated to routing resources. The multi-valued tracks are slightly more susceptible to process variation. We present a layout method for multivalued standard cells and determine the layout overhead.We conclude with various usage scenarios of these tracks.

Domaines

Electronique

Dates et versions

hal-02287527 , version 1 (13-09-2019)

Identifiants

Citer

Sumanta Chaudhuri, Tarik Graba, Yves Mathieu. Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. 2019. ⟨hal-02287527⟩
47 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More