A Statistical Method for Transistor Ageing and Process Variation Applied to Reliability Simulation

Hao Cai 1, 2 H. Petit 3, 2 J. F. Naviner
1 SSH - Secure and Safe Hardware
LTCI - Laboratoire Traitement et Communication de l'Information
3 C2S - Circuits et Systèmes de Communication
LTCI - Laboratoire Traitement et Communication de l'Information
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Submitted on : Friday, September 13, 2019 - 3:37:23 PM
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  • HAL Id : hal-02286335, version 1

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Hao Cai, H. Petit, J. F. Naviner. A Statistical Method for Transistor Ageing and Process Variation Applied to Reliability Simulation. 3rd European Workshop on CMOS variability, Jun 2012, Nice – Sophia Antipolis, France. ⟨hal-02286335⟩

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