A General Cost-effective Design Structure for Probabilistic-Based Noise-Tolerant Logic Functions in Nanometer CMOS Technology

Kaikai Liu 1, 2 Ting An 1, 2 Hao Cai 1, 2 Lirida Alves de Barros Naviner 1, 2 Jean-François Naviner Hervé Petit 3, 2
1 SSH - Secure and Safe Hardware
LTCI - Laboratoire Traitement et Communication de l'Information
3 C2S - Circuits et Systèmes de Communication
LTCI - Laboratoire Traitement et Communication de l'Information
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https://hal.telecom-paristech.fr/hal-02286855
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Submitted on : Friday, September 13, 2019 - 4:16:44 PM
Last modification on : Thursday, October 17, 2019 - 12:37:03 PM

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Kaikai Liu, Ting An, Hao Cai, Lirida Alves de Barros Naviner, Jean-François Naviner, et al.. A General Cost-effective Design Structure for Probabilistic-Based Noise-Tolerant Logic Functions in Nanometer CMOS Technology. Eurocon 2013, Jul 2013, Zagreb, Croatia. pp.1829-1836, ⟨10.1109/EUROCON.2013.6625225⟩. ⟨hal-02286855⟩

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