# Eager Stack Cache Memory Transfers

2 ACES - Autonomic and Critical Embedded Systems
LTCI - Laboratoire Traitement et Communication de l'Information
Abstract :

The growing complexity of modern computer architectures increasingly complicates the prediction of the run-time behavior of software. For real-time systems, where a safe estimation of the program's worst-case execution time is needed, time-predictable computer architectures promise to resolve this problem. The stack cache, for instance, allows the compiler to efficiently cache a program's stack, while static analysis of its behavior remains easy.

This work introduces an optimization of the stack cache that allows to anticipate memory transfers that might be initiated by future stack cache control instructions. These eager memory transfers thus allow to reduce the average-case latency of those control instructions, very similar to prefetching'' techniques known from conventional caches. However, the mechanism proposed here is guaranteed to have no impact on the worst- case execution time estimates computed by static analysis. Measurements on a dual-core platform using the Patmos processor and time-division-multiplexing-based memory arbitration, show that our technique can eliminate up to 62% (7%) of the memory transfers from (respectively to) the stack cache on average over all programs of the MiBench benchmark suite.

Keywords :
Document type :
Conference papers
Domain :

https://hal.telecom-paristech.fr/hal-02287376
Contributor : Telecomparis Hal <>
Submitted on : Friday, September 13, 2019 - 4:54:38 PM
Last modification on : Wednesday, October 16, 2019 - 4:00:04 PM

### Identifiers

• HAL Id : hal-02287376, version 1

### Citation

Naji Amine, Florian Brandner. Eager Stack Cache Memory Transfers. Workshop on Worst-Case Execution Time Analysis, Jul 2016, Toulouse, France. ⟨hal-02287376⟩

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