Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology

Sumanta Chaudhuri 1, 2 Tarik Graba 1, 2 Yves Mathieu 1, 2
1 SSH - Secure and Safe Hardware
LTCI - Laboratoire Traitement et Communication de l'Information
Abstract :

In this paper we present quaternary and ternary routing tracks for FPGAs, and their implementation in 28nm FDSOI technology. We discuss the transistor level design of multi-valued repeaters, multiplexers and translators, and specific features of FDSOI technology which make it possible. Next we compare the multi-valued routing architectures with equivalent single driver two-valued routing architectures. We show that for long tracks, it is possible to achieve upto 3x reduction in dynamic switching energy, upto 2x reduction in routing wire area and 10% reduction in area dedicated to routing resources. The multi-valued tracks are slightly more susceptible to process variation. We present a layout method for multivalued standard cells and determine the layout overhead.We conclude with various usage scenarios of these tracks.

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Preprints, Working Papers, ...
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https://hal.telecom-paristech.fr/hal-02287527
Contributor : Telecomparis Hal <>
Submitted on : Friday, September 13, 2019 - 5:04:03 PM
Last modification on : Thursday, October 17, 2019 - 12:37:03 PM

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  • HAL Id : hal-02287527, version 1
  • ARXIV : 1609.08681

Citation

Sumanta Chaudhuri, Tarik Graba, Yves Mathieu. Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. 2019. ⟨hal-02287527⟩

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