Optimal Asymmetrical Back Plane Biasing for Energy Efficient Digital Circuits in 28 nm UTBB FD-SOI

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https://hal.telecom-paristech.fr/hal-02287634
Contributor : Telecomparis Hal <>
Submitted on : Friday, September 13, 2019 - 5:09:58 PM
Last modification on : Thursday, October 17, 2019 - 12:37:03 PM

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  • HAL Id : hal-02287634, version 1

Citation

Francisco Veirano, Lirida Alves de Barros Naviner, Fernando Silveira. Optimal Asymmetrical Back Plane Biasing for Energy Efficient Digital Circuits in 28 nm UTBB FD-SOI. Integration, the VLSI Journal, 2017. ⟨hal-02287634⟩

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