Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits

Francisco Veirano; Lirida Alves de Barros Naviner; Fernando Silveira

Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits

Francisco Veirano Lirida Alves de Barros Naviner ^{1, 2} Fernando Silveira

1 SSH - Secure and Safe Hardware

LTCI - Laboratoire Traitement et Communication de l'Information

2 COMELEC - Département Communications & Electronique

Document type :

Journal articles

Domain :

Engineering Sciences [physics] / Micro and nanotechnologies/Microelectronics

Engineering Sciences [physics] / Electronics

Complete list of metadatas

https://hal.telecom-paristech.fr/hal-02287635
Contributor : Telecomparis Hal <>
Submitted on : Friday, September 13, 2019 - 5:10:00 PM
Last modification on : Sunday, September 15, 2019 - 1:11:51 AM

Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits

Identifiers

Collections

Citation

Export

Metrics

3

Contact

Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits

Identifiers

Collections

Citation

Export

Share

Metrics

3

Contact