Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits

Complete list of metadatas

https://hal.telecom-paristech.fr/hal-02287635
Contributor : Telecomparis Hal <>
Submitted on : Friday, September 13, 2019 - 5:10:00 PM
Last modification on : Thursday, October 17, 2019 - 12:37:03 PM

Identifiers

  • HAL Id : hal-02287635, version 1

Citation

Francisco Veirano, Lirida Alves de Barros Naviner, Fernando Silveira. Optimum NMOS/PMOS Imbalance for Energy Efficient Digital Circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 2017. ⟨hal-02287635⟩

Share

Metrics

Record views

8