Nouvelle architecture de BLE tolérante aux fautes dans les FPGAs SRAM

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Submitted on : Saturday, September 14, 2019 - 6:44:18 PM
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Arwa Ben Dhia, Lirida Alves de Barros Naviner, Philippe Matherat. Nouvelle architecture de BLE tolérante aux fautes dans les FPGAs SRAM. Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM), Jun 2013, Grenoble, France. ⟨hal-02288374⟩

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