A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement

Document type :
Conference papers
Complete list of metadatas

https://hal.telecom-paristech.fr/hal-02412244
Contributor : Telecomparis Hal <>
Submitted on : Sunday, December 15, 2019 - 12:52:10 PM
Last modification on : Wednesday, January 8, 2020 - 1:05:42 AM

Identifiers

Collections

Citation

Daisuke Fujimoto, Makoto Nagata, Shivam Bhasin, Jean-Luc Danger. A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement. ASP-DAC, Jan 2015, Tokyo, Japan. ⟨10.1109/ASPDAC.2015.7059100⟩. ⟨hal-02412244⟩

Share

Metrics

Record views

4